An analog-to-digital converter (A/D or ADC) is an electronic device that can convert analog signal information (e.g. amplitude or phase) to a digital (e.g. numerical) value representative of the analog signal. These devices enable a central processing unit to carry out processing functions in a more quantized mathematical domain without the need for downstream analog devices.
Signal processing systems utilizing A/D converters, including complex A/D converters (CADCs), have various functionality requirements. Such requirements may include a track and hold, or sample and hold operation performed on an analog input signal, as well as precise timing operations, in addition to the A/D conversion process. Clock generators, for example, are used to synchronize sample and hold amplifiers with an ADC. The sample and hold amplifiers follow an input analog signal of interest until a control signal from the clock causes the amplifier to freeze and hold the time varying analog signal (for a given time interval). The same clock signal also strobes the ADC to convert the held or “frozen” sample to a digital value. This digital data can then be buffered and read out to memory for further processing. The time it takes for the sample and hold amplifiers and ADC to perform the operation and be ready for the next value is the ND sample rate.
Standard A/D conversion systems are too slow to directly digitize ultra high frequency and microwave RF signals. These frequency ranges are typically in the second and third Nyquist regions of the converter, including military frequency bands up to 20-40 GHz. Accordingly, these systems must utilize several analog down conversion steps before the signal is sufficiently low in frequency to allow for digitization. In addition to limited or low sample rates, A/D converters further hinder signal processing operations due to their limited resolution, measured by the effective number of bits or ENOB. In order to improve ADC resolution, various architectures including pipeline ADCs have been developed. Digitally programmable ADCs have been developed to support certain processing requirements such as multi-band and multi-mode operation. One such example is a digitally programmable sub-ranging ADC, which incorporates the improved resolution of pipeline-based architectures with the ability to operate in various modes (e.g. 5 bit, 9 bit and 13 bit). Traditional ADC clocking schemes, including ramp-based timing circuits, are limited both in their ability to accurately track, as well as their ability to operate at sampling frequencies over a wide bandwidth.
Alternative variable clock architectures that support low-noise operation over both high and low frequencies (e.g. over a decade of coverage) are desired.